module pin(
	input              wsignl,
	input   [31:0]     addr,
	input   [31:0]     wdata,


	output  [31:0]     o
);

reg   [31:0]       reg_o;
assign o = reg_o;

always @(*) begin
	if (addr >= 32'b100000000000 && addr <= 32'b100000001111) begin
		if(wsignl) reg_o <= wdata;
	end
end

endmodule

